Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor memory device which receives data and a data strobe signal which are transferred from a chipset, and performs a write operation with the data.
In general, semiconductor memory devices, such as double data rate synchronous dynamic random access memory (DDR SDRAM), use a data strobe signal to accurately recognize input data. The data strobe signal is outputted with data from a chipset, such as a memory controller, and toggles with the data. Signals transferred to a semiconductor memory device from a chipset include an external clock signal. Since the external clock signal and data are transferred through transfer lines having different loads, the two signals may be transferred at different speeds. Accordingly, it is not easy to recognize the data by using the external clock signal. Therefore, the chipset transfers a data strobe signal to the semiconductor memory device through a transfer line having a similar load to that of the transfer line through which the data is transferred. The semiconductor memory device may accurately recognize the data by using the data strobe signal transferred in such a manner. The data strobe signal should guarantee a setup time and a hold time with respect to the data, and is generally composed of a data strobe signal and a data strobe bar signal.
FIG. 1 is a timing diagram illustrating the effects of a write operation on signals of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device receives an external clock signal CLK, a data strobe signal DQS, a data strobe bar signal DQSB, and data DAT from an external chipset. In an idle state, the data strobe signal DQS and the data strobe bar signal DQSB maintain a termination level which corresponds to a half of the voltage level of a power supply voltage. After a preamble period, the data strobe signal DQS and the data strobe bar signal DQSB start to toggle with the data DAT. For reference, during the preamble period, the data strobe signal DQS maintains a logic ‘low’ level and the data strobe bar signal DQSB maintains a logic ‘high’ level. During a toggling period, the data strobe signal DQS and the data strobe bar signal DQSB swing in a narrow range on the basis of the termination level. That is, the termination level is the center voltage level of a high voltage level and a low voltage level that the data strobe signal DQS and the data strobe bar signal DQSB swing or toggle between.
Meanwhile, the semiconductor memory device internally buffers the data strobe signal DQS and the data strobe bar signal DQSB which are inputted from the external chipset, and generates a rising data strobe signal DQSR corresponding to the data strobe signal DQS and a falling data strobe signal DQSF corresponding to the data strobe bar signal DQSB. The data DAT are latched and shifted according to the rising data strobe signal DQSR and the falling data strobe signal DQSF, and outputted as zeroth to third alignment signals ALGN0 to ALGN3.
As shown in FIG. 1, the data DAT corresponding to the rising data strobe signal DQSR (that is, data R0, R1, R2, and R3) are latched in response to the rising data strobe signal DQSR. Then, the latched data are shifted and the data DAT corresponding to the falling data strobe signal DQSF (that is, data F0, F1, F2, and F3) are latched, in response to the falling data strobe signal DQSF. In other words, the data DAT, which are sequentially inputted, are aligned as the zeroth to third alignment signals ALGN0 to ALGN3 in response to the rising data strobe signal DQSR and the falling data strobe signal DQSF.
Meanwhile, the semiconductor memory device performs a variety of operations corresponding to various operation modes. Such operation modes may depend on a burst length. The burst length corresponds to the number of data which are received at a time by one data pin. When the burst length is four, it means that four data are received. When the burst length is eight, it means that eight data are received. The semiconductor device internally generates a signal depending on such a burst length. The signal is referred to as a data input strobe signal.
Hereafter, a case in which the burst length is eight will be described with reference to FIG. 1.
The data DAT which are consecutively applied are latched and shifted in response to the rising data strobe signal DQSR and the falling data strobe signal DQSF. At this time, when a first data input strobe signal DISTBP_BL4 is activated, data R0, F0, R1, and F1 of the zeroth to third alignment signals ALGN0 to ALGN3 are latched as fourth to seventh alignment signals ALGN<4:7>. Subsequently, the data DAT are latched and shifted one more time, in response to the rising data strobe signal DQSR and the falling data strobe signal DQSF. At this time, when a second data input strobe signal DISTBP_BL8 is activated, the data R0, F0, R1, and F1 of the fourth to seventh alignment signals ALGN<4:7> and data R2, F2, R3, and F3 of the zeroth to third alignment signals ALGN0 to ALGN3 are outputted to corresponding global data lines GIO<0:7>.
For reference, when the burst length is four, the semiconductor memory device outputs the data R0, F0, R1, and F1, respectively transferred as the zeroth to third alignment signals ALGN0 to ALGN3, to the corresponding global data lines, in response to the second data input strobe signal DISTBP_BL8.
As described above, the data R0, F0, R1, and F1 of the zeroth to third alignment signals ALGN0 to ALGN3 are synchronized in response to the first data input strobe signal DISTBP_BL4, and the data R2, F2, R3, and F3 are synchronized in response to the second data input strobe signal DISTBP_BL8. Ideally, the period of time between the first data input strobe signal DISTBP_BL4 and the second data input strobe signal DISTBP_BL8 is one cycle (1 tCK) of the external clock signal CLK. Significantly, however, a skew with respect to the external clock signal CLK occurs in the data strobe signal DQS and the data strobe bar signal DQSB. Hereinafter, the specification refers to the margin of time that the data strobe signal DQS lags or leads the external clock signal CLK as ‘tDQSS’. Further, hereinafter, tDQSS is defined as ±¼ of one cycle (1 tCK) of the external clock signal CLK. Therefore, the synchronization operation may be performed by the first data input strobe signal DISTBP_BL4 and the second data input strobe signal DISTBP_BL8 within a time margin of 0.5 tCK.
Such a time margin of 0.5 tCK may make it difficult to perform the synchronization operation according to the first data input strobe signal DISTBP_BL4 and the second data input strobe signal DISTBP_BL8. Furthermore, as the operation frequency of the semiconductor memory device increases, a pulse period corresponding to 1 tCK gradually decreases. Therefore, an actual time margin further decreases. As a result, when the synchronization operation according to the first data input strobe signal DISTBP_BL4 and the second data input strobe signal DISTBP_BL8 is not normally performed, an operation error of the semiconductor memory device may result.